National Yang Ming Chiao Tung University | Taiwan
Dr. Sekhar Reddy Kola is a Postdoctoral Fellow in the Department of Electrical and Computer Engineering at National Yang Ming Chiao Tung University (NYCU), Taiwan. He earned his Ph.D. in Semiconductor Devices from NYCU, where he focused on the process variation effect and intrinsic parameter fluctuation of vertically stacked gate-all-around (GAA) silicon nanosheet complementary field-effect transistors (CFETs) under the supervision of Prof. Yiming Li. With a solid academic foundation, including an M.Sc. in Electronics and a B.S. in Mathematics, Electronics, and Computer Science from Sri Venkateswara University, India, Dr. Kola has made significant contributions to the field of semiconductor device physics and modeling. His research interests encompass GAA nanosheet and nanowire FETs, CFET design, statistical process variation modeling, reliability analysis, and machine learning applications in nanoelectronics. He has published 33 documents with over 311 citations and an h-index of 10, reflecting his impactful scientific contributions. Dr. Kola has received several honors, including the Best Paper Award at IEDMS 2018 and the Outstanding Foreign Student Scholarship from NYCU. Through his innovative research on nanoscale device modeling and variability analysis, Dr. Kola continues to advance the development of next-generation semiconductor technologies for sub-1-nm nodes.
Featured Publications
Kola, S. R., & Li, Y. (2025). Effects of bottom channel coverage ratio on leakage current and static power consumption of vertically stacked GAA Si NS FETs. ECS Journal of Solid State Science and Technology, 14(2), 025001.
Kola, S. R., Li, Y., & Butola, R. (2024). Statistical device simulation and machine learning of process variation effects of vertically stacked gate-all-around Si nanosheet CFETs. IEEE Transactions on Nanotechnology, 23, 386–392.
Kola, S. R., & Li, Y. (2023). Electrical characteristic and power fluctuations of GAA Si NS CFETs by simultaneously considering six process variation factors. IEEE Open Journal of Nanotechnology, 4, 112–120.
Sreenivasulu, V. B., Kumari, N. A., Kola, S. R., Singh, J., & Li, Y. (2023). Exploring the performance of 3-D nanosheet FET in inversion and junctionless modes: Device and circuit-level analysis and comparison. IEEE Access, 11, 42256–42265.
Kola, S. R., Li, Y., & Thoti, N. (2020). Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type MOSFETs. Japanese Journal of Applied Physics, 59(SGGA02).